A successful candidate will develop architecture/microarachitectures, develop and/or extend existing RTL code base, write and debug unit-level testbenches and testcases (there is a separate Verification Team) and perform Lab Debug for high performance FPGAs used in a flow state aware router. Experience in a diverse number of sucessful ASIC and FPGA Development projects in IP Networking is highly desireable.
The candidates primary job functions will be to:
Specify and document microarchitecture for block level designs in FPGAs used in an IP networking environment.
RTL coding using Verilog
Write testbenches and testcases for block level tests
Verilog simulation using Questasim
Synthesize and generate bitfiles targeted to Xlinx Virtex-6 using Xilinx ISE Flow
Debug in the Lab using Xilinx Chipscope and Ixia test equipment
Scripting as needed (Make, Tcl, Perl)
Job Requirements:
Strong ASIC/FPGA design background
Experience with Xilinx Virtex-4 or Virtex-5 FPGA families.
Strong experience in Xilinx ISE flow preferred
Extensive experience with Verilog simulators (Questasim, VCS or NC-Verilog)
Prior experience working in a Linux-based development environment.
Lab Debug experience using Xilinx Chipscope
Experience with Ixia test equipment preferred.
Experience with Memory Interfaces specifically DDR2 or DDR3 is highly desirable for the candiates first project.
Strong experience in Gigabit Ethernet, IP and TCP is preferred
Strong written and verbal communications skills
Ability to architect as well as implement
Good Team Player and a self-starter
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